InterPRET: a Time-predictable Multicore Processor

Author(s): Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Jerad, Chadlia and Wang, Edward and Lohstroh, Marten and Lee, Edward A. and Schoeberl, Martin

Abstract
With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-on-chip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems.

Electronic Downloads

• https://doi.org/10.1145/3576914.3587497

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Citation Formats

• APA
  

                  
  Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Jerad, Chadlia and Wang, Edward and Lohstroh, Marten and Lee, Edward A. and Schoeberl, Martin. (2023). InterPRET: a Time-predictable Multicore Processor. In Workshop on Time-Centric Reactive Systems (TCRS), CPS-IoT Week Workshops, San Antonio, TX, USA.  doi:10.1145/3576914.3587497.                     
                  
                  

• MLA
  

                  
  Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Jerad, Chadlia and Wang, Edward and Lohstroh, Marten and Lee, Edward A. and Schoeberl, Martin. "InterPRET: a Time-predictable Multicore Processor." Workshop on Time-Centric Reactive Systems (TCRS), CPS-IoT Week Workshops, San Antonio, TX, USA, 2023.  doi:10.1145/3576914.3587497.                     
                  
                  

• Chicago
  

                  
  Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Jerad, Chadlia and Wang, Edward and Lohstroh, Marten and Lee, Edward A. and Schoeberl, Martin. "InterPRET: a Time-predictable Multicore Processor." Workshop on Time-Centric Reactive Systems (TCRS), CPS-IoT Week Workshops, San Antonio, TX, USA, 2023.  doi:10.1145/3576914.3587497.                     
                  
                  

• BibTeX
  

                      
  @inproceedings{JellumEtAl:23:InterPRET,
  	author = {Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Jerad, Chadlia and Wang, Edward and Lohstroh, Marten and Lee, Edward A. and Schoeberl, Martin},
  	title = {InterPRET: a Time-predictable Multicore Processor},
  	booktitle = {Workshop on Time-Centric Reactive Systems (TCRS), CPS-IoT Week Workshops, San Antonio, TX, USA},
  	month = {May 9},
  	year = {2023},
  	doi = {10.1145/3576914.3587497},
  	abstract = {With the end of Moore's law and the breakdown of Dennard scaling, multicore processors are the standard way to continue improving performance while reducing Size, Weight and Power (SWaP). However, this performance is typically achieved at the cost of repeatability and predictability. Precision-timed (PRET) architectures have been shown to deliver high performance without sacrificing predictability. In this paper, we introduce InterPRET: an architecture consisting of FlexPRET cores interconnected via the S4NOC network-on-chip. Both the processor cores and the network-on-chip are time-predictable, yielding an end-to-end time-predictable architecture suitable for real-time systems.},
  	URL = {https://doi.org/10.1145/3576914.3587497}}